The present invention relates generally to CMOS device fabrication processes and, more particularly, to a method of for fabricating sacrificial oxide layers at a low thermal budget to avoid undesired thermally induced diffusion of doped regions and to reduce defect levels in a silicon substrates thereby improving semiconductor device performance.
Fabrication of metal-oxide-semiconductor (MOS) integrated circuits involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is typically formed on a silicon semiconductor substrate having a channel region which is doped with either n-type or p-type impurities. For example, in the formation of a MOS field effect transistor (MOSFET) the gate structure is formed by first forming a gate dielectric over the silicon substrate followed by the formation of a polysilicon or other conducting material gate electrode over the gate dielectric. Dopant impurities are then introduced into the silicon substrate to form various doped regions including source and drain regions. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern integrated circuit microelectronic devices employ features having critical dimensions of Less than 0.25 microns requiring a concomitant scaling down of feature sizes such as gate structures. For example, many modern integrated circuit microelectronic processes are now producing semiconductor devices having CD""s of less than 0.13 microns. As device sizes decrease, the size of device components such as transistors, including gate oxide thickness, also decreases. Fabrication of smaller device components allows more device components to be placed on a given substrate area, Thereby allowing relatively large integrated circuit systems to be incorporated on a single die area.
In semiconductor fabrication, silicon dioxide (SiO2) is commonly used as a gate dielectric formed as a thin layer overlying a silicon substrate in the formation of various semiconductor devices including metal-oxide-semiconductor (MOS) transistors. As device dimensions have been scaled down, the thickness of the SiO2 layer has also decreased to maintain the same capacitance between the gate electrode and channel regions. A gate oxide layer thickness of less than about 20 Angstroms is frequently a standard design limitation for 0.13 micron and smaller integrated circuit microelectronic fabrication to achieve required capacitances.
With the formation of thinner gate oxides, the presence of defects, including point and line defects (dislocations) at the oxide/silicon interface become more important as such defects form charge trapping and interfacial states which more readily alter the functioning of the semiconductor device. In prior art integrated circuit fabrication processes, a thin SiO2 layer, also referred to as a pad oxide, initial oxide, or sacrificial oxide, is thermally grown over exposed portions of a silicon substrate having a thickness of about 100 to 150 Angstroms. The sacrificial oxide serves several purposes including protecting the underlying silicon substrate from chemical contamination during subsequent processing steps, for example, acting as an etch stop during phosphoric acid stripping of an overlying nitride layer following shallow trench isolation (STI) formation. In addition, sacrificial oxide layers protect the silicon from excessive damage during ion implantation steps by controlling the depth of ion implantation and reducing ion channeling effects. Further, sacrificial oxide layers act to relieve induced stresses and defects present in the underlying silicon substrate. For example following an STI etching process a sacrificial oxide layer is deposited within the trenches to remove surface defects and improve the interface between the oxide and the silicon substrate.
Common in the art of semiconductor integrated circuit microelectronic fabrication processes is the formation of sacrificial oxide layers which are thermally grown at temperatures from about 800xc2x0 C. to about 1000xc2x0 C., for example by rapid thermal oxidation (RTO) processes to minimize the time at elevated temperatures which tends to cause the formation of defects such as dislocations at the SiO2/silicon interface. Typically sacrificial oxide layers are formed at elevated temperatures and removed prior to the formation of the gate oxide thereby avoiding any significant impact on thermally sensitive regions such as subsequently formed doped regions including LDD regions and source/drain regions. For example, ion implantations to form doped regions typically include several carefully controlled ion implantations at pre-determined depths followed by carefully controlled annealing processes to distribute the dopants. The formation of sacrificial oxide layers at typical elevated temperatures following the formation of doped regions would detrimentally alter the electrical functioning of the semiconductor device. In addition, the formation of sacrificial oxide layers prior to gate oxide formation tends to contribute to defect formation at the gate/oxide interface to detrimentally affect gate oxide integrity (GOI) by creating trapping and interfacial charged states which alter device functioning. In addition, dielectric breakdown of the gate oxide may occur at lower values of gate voltage as a result of defects at the silicon/SiO2 interface.
Also common in the art of semiconductor integrated circuit microelectronic fabrication is the fabrication of embedded DRAM and SRAM devices logic devices and memory devices are simultaneously incorporated requiring the formation of doped regions prior to the formation of the gate oxide. In this respect, the thermal budget, defined as the integrated time a semiconductor process wafer is at a particular temperature is necessarily restricted to avoid inducing undesirable diffusion of implanted dopants in doped regions to thereby detrimentally alter the electrical functioning of the device. For example, it is preferable to limit the maximum temperature the device is exposed to elevated temperatures prior to gate formation to not more than about 650xc2x0 C. As a result, conventional methods to form thermally grown oxides at temperatures exceeding about 650xc2x0 C. are unacceptable requiring new processing methods with lower thermal budgets to form sacrificial oxide layers.
Therefore it would be advantageous to develop a method in the semiconductor integrated circuit microelectronic fabrication are for forming sacrificial silicon dioxide layers using a lower thermal budget manufacturing process.
It is therefore an object of the invention to provide a method in the semiconductor integrated circuit microelectronic fabrication art for forming sacrificial silicon dioxide layers using a lower thermal budget manufacturing process while overcoming other limitations and shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a silicon dioxide layer over a silicon substrate.
In a first embodiment, the method includes providing a substrate having exposed silicon portions; and forming a silicon dioxide layer over the exposed silicon portions according to an oxide formation process including contacting the exposed silicon portions with an oxidizing solution comprising water and ozone.
In related embodiments, the method includes removing at least a portion of the silicon dioxide layer according to an oxide removal process comprising contacting the silicon dioxide layer with an oxide etching solution and sequentially repeating the oxide formation process and the oxide removal process to form newly exposed silicon portions.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.